The present invention relates generally to memories, and, more particularly, to an error detection system for a memory.
Memories such as dynamic random-access memories (DRAMs), double-data-rate (DDR) memories, and static random-access memories (SRAMs) are used to store information such as instructions and data packets. A processor fetches instructions and data packets from a memory and processes the data packets using the instructions. The processor also stores processed data packets in memory.
The processor and memories, along with multiple other circuits, may be integrated on a single semiconductor chip or integrated circuit (IC). The IC is packaged to prevent physical damage and corrosion thereto. However, the packaging material may contain small amounts of radioactive contaminants that decay and release alpha particles that can disturb the distribution of electrons in the semiconductor material from which the IC is formed. The disturbances can change the logic states of bits stored in the memories. Such an error is referred to as a soft error. Further, cosmic rays, thermal neutrons, random noise, and capacitive and inductive cross-talk can cause errors in the bits stored in the memories.
A known technique to overcome soft errors is to use an error detection system. When a memory receives a data packet, the error detection system calculates an error bit for the data packet and stores the error bit along with the data packet. When the data packet is read from the memory, the error detection system again calculates an error bit corresponding to the read data and compares it with the stored error bit to determine if there is an error in the data packet. However, the calculation logic and space for storing the error bits results in an increase in circuit area.
Implementation of a memory as a first-in first-out (FIFO) aids in reduction of the area required to store the error bits because the processor can access the data packets stored in the FIFO memory sequentially. The processor stores a data packet in the FIFO memory during a write cycle and fetches the data packet from the FIFO memory during a read cycle. The error detection system includes read and write signature generation circuits. The read signature generation circuit calculates a read signature based on data packets read from the FIFO memory, while the write signature generation circuit calculates a write signature based on data packets written to the FIFO memory. When the FIFO memory is empty, i.e., when the read and write addresses are the same and there is no data packet to be read, the read signature is compared with the write signature and if they are not equal, an error signal is generated. However, for the error detection system to compare the write and read signatures, the FIFO memory must be empty. When the FIFO memory is not empty, the FIFO memory halts the write cycles until it is empty, which delays storing new data packets in the FIFO memory.
It would be advantageous to have an error detection system that detects an error in a data packet stored in a FIFO memory irrespective of the FIFO memory being empty, and without interrupting the read and write cycles of the FIFO memory.